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From EDApedia
Currently we are working on the collection of EDA grand challenging problems and your feedback and contribution will be appreciated.
The website is iniatied by IEEE Council on Electronic Design Automation (CEDA) under the guidance from Dr. Jinjun Xiong (IBM T. J. Watson Research Center).
It is initially developed by Prof. Yiyu Shi (Missouri University of Science and Technology, formerly University of Missouri, Rolla).
Thanks.
Archived Grand Challenge List
- CEDA0001 - Wirelength-driven Standard-Cell Placement
- CEDA0002 - Wirelength-driven Standard-Cell Placement
Open Hot Topics
- All Topics
- Topics Sorted by Categories (based on The ACM Computing Classification System (1998))
Hot Topics Ranking
| Topic | Importance | Difficulty | Well-defined | Average |
|---|---|---|---|---|
| Global Routing | 4.00 | 4.00 | 4.50 | 4.17 |
| Clock Network Synthesis | 3.75 | 4.00 | 4.50 | 4.08 |
| Wirelength-driven Standard-Cell Placement | 4.33 | 4.00 | 3.33 | 3.89 |
| Power Gating | 4.00 | 3.00 | 4.00 | 3.67 |
| Partitioning | 3.33 | 3.50 | 3.33 | 3.39 |
| 3DIC Thermal Management | 3.33 | 3.67 | 3.00 | 3.33 |
| Stochastic Behavioral Modeling | 4.00 | 3.00 | 3.00 | 3.33 |
| Through Silicon Via and Cell Co-Placement | 2.50 | 3.33 | 3.33 | 3.06 |
| Static Timing Analysis | 3.00 | 2.00 | 4.00 | 3.00 |
| Multi-Voltage Mode Clock Skew Minimization | 2.50 | 3.50 | 2.50 | 2.83 |
